This design is targeted for xczu3eg board (part number: xczu3eg-sfvc784-1-e)

Zynq UltraScale+ Design Summary

Device	xczu3eg
SpeedGrade	-1
Part	xczu3eg-sfvc784-1-e
Description	Zynq UltraScale+ PS Configuration Report
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction	Drive Strength(mA)
MIO 0	Quad SPI Flash	sclk_out	cmos	slow	pullup	out	12
MIO 1	Quad SPI Flash	miso_mo1	schmitt	slow	pullup	inout	12
MIO 2	Quad SPI Flash	mo2	schmitt	slow	pullup	inout	12
MIO 3	Quad SPI Flash	mo3	schmitt	slow	pullup	inout	12
MIO 4	Quad SPI Flash	mosi_mi0	schmitt	slow	pullup	inout	12
MIO 5	Quad SPI Flash	n_ss_out	cmos	slow	pullup	out	12
MIO 6	Feedback Clk	clk_for_lpbk	cmos	slow	pullup	out	12
MIO 7	Quad SPI Flash	n_ss_out_upper	cmos	slow	pullup	out	12
MIO 8	Quad SPI Flash	mo_upper[0]	schmitt	slow	pullup	inout	12
MIO 9	Quad SPI Flash	mo_upper[1]	schmitt	slow	pullup	inout	12
MIO 10	Quad SPI Flash	mo_upper[2]	schmitt	slow	pullup	inout	12
MIO 11	Quad SPI Flash	mo_upper[3]	schmitt	slow	pullup	inout	12
MIO 12	Quad SPI Flash	sclk_out_upper	cmos	slow	pullup	out	12
MIO 13	GPIO0 MIO	gpio0[13]	schmitt	slow	pullup	inout	12
MIO 14	GPIO0 MIO	gpio0[14]	schmitt	slow	pullup	inout	12
MIO 15	GPIO0 MIO	gpio0[15]	schmitt	slow	pullup	inout	12
MIO 16	GPIO0 MIO	gpio0[16]	schmitt	slow	pullup	inout	12
MIO 17	GPIO0 MIO	gpio0[17]	schmitt	slow	pullup	inout	12
MIO 18	GPIO0 MIO	gpio0[18]	schmitt	slow	pullup	inout	12
MIO 19	GPIO0 MIO	gpio0[19]	schmitt	slow	pullup	inout	12
MIO 20	GPIO0 MIO	gpio0[20]	schmitt	slow	pullup	inout	12
MIO 21	GPIO0 MIO	gpio0[21]	schmitt	slow	pullup	inout	12
MIO 22	UART 0	rxd	schmitt	fast	pullup	in	12
MIO 23	UART 0	txd	cmos	slow	pullup	out	12
MIO 24	GPIO0 MIO	gpio0[24]	schmitt	slow	pullup	inout	12
MIO 25	GPIO0 MIO	gpio0[25]	schmitt	slow	pullup	inout	12
MIO 26			schmitt	slow	pullup	in	12
MIO 27			schmitt	slow	pullup	in	12
MIO 28			schmitt	slow	pullup	out	12
MIO 29			schmitt	slow	pullup	in	12
MIO 30			schmitt	slow	pullup		12
MIO 31			schmitt	slow	pullup	out	12
MIO 32			schmitt	slow	pullup		12
MIO 33			schmitt	slow	pullup		12
MIO 34			schmitt	slow	pullup		12
MIO 35			schmitt	slow	pullup		12
MIO 36			schmitt	slow	pullup		12
MIO 37			schmitt	slow	pullup		12
MIO 38			schmitt	slow	pullup	inout	12
MIO 39			schmitt	slow	pullup	inout	12
MIO 40			schmitt	slow	pullup		12
MIO 41			schmitt	slow	pullup		12
MIO 42			schmitt	slow	pullup	in	12
MIO 43			schmitt	slow	pullup	out	12
MIO 44			cmos	slow	disable	in	12
MIO 45			cmos	slow	disable	in	12
MIO 46			cmos	slow	disable	inout	12
MIO 47			cmos	slow	disable	inout	12
MIO 48			cmos	slow	disable	inout	12
MIO 49			cmos	slow	disable	inout	12
MIO 50			cmos	slow	disable	inout	12
MIO 51			schmitt	slow	disable	out	12
MIO 52			schmitt	slow	pullup	in	12
MIO 53			schmitt	slow	pullup	in	12
MIO 54			schmitt	slow	pullup	inout	12
MIO 55			schmitt	slow	pullup	in	12
MIO 56			schmitt	slow	pullup	inout	12
MIO 57			schmitt	slow	pullup	inout	12
MIO 58			schmitt	slow	pullup	out	12
MIO 59			schmitt	slow	pullup	inout	12
MIO 60			schmitt	slow	pullup	inout	12
MIO 61			schmitt	slow	pullup	inout	12
MIO 62			schmitt	slow	pullup	inout	12
MIO 63			schmitt	slow	pullup	inout	12
MIO 64	Gem 3	rgmii_tx_clk	cmos	slow	pullup	out	12
MIO 65	Gem 3	rgmii_txd[0]	cmos	slow	pullup	out	12
MIO 66	Gem 3	rgmii_txd[1]	cmos	slow	pullup	out	12
MIO 67	Gem 3	rgmii_txd[2]	cmos	slow	pullup	out	12
MIO 68	Gem 3	rgmii_txd[3]	cmos	slow	pullup	out	12
MIO 69	Gem 3	rgmii_tx_ctl	cmos	slow	pullup	out	12
MIO 70	Gem 3	rgmii_rx_clk	schmitt	fast	pullup	in	12
MIO 71	Gem 3	rgmii_rxd[0]	schmitt	fast	pullup	in	12
MIO 72	Gem 3	rgmii_rxd[1]	schmitt	fast	pullup	in	12
MIO 73	Gem 3	rgmii_rxd[2]	schmitt	fast	pullup	in	12
MIO 74	Gem 3	rgmii_rxd[3]	schmitt	fast	pullup	in	12
MIO 75	Gem 3	rgmii_rx_ctl	schmitt	fast	pullup	in	12
MIO 76	MDIO 3	gem3_mdc	cmos	slow	pullup	out	12
MIO 77	MDIO 3	gem3_mdio_out	schmitt	slow	pullup	inout	12

PS Clocks information

PSS REF CLK : 33.333

Name	Source	Input Frequency (MHz)
APLL	PSS_REF_CLK	2100.000
DPLL	PSS_REF_CLK	2400.000
VPLL	PSS_REF_CLK	3000.000
RPLL	PSS_REF_CLK	2800.000
IOPLL	PSS_REF_CLK	3000.000

Peripheral	Requested Frequency (MHz)	Source	Actual Frequency (MHz)
GEM3 freq (MHz)	125	IOPLL	124.999977
QSPI freq (MHz)	300	IOPLL	299.999939
UART0 freq (MHz)	100	IOPLL	99.999985
I2C0 freq (MHz)	100	IOPLL	99.999985
SPI0 freq (MHz)	200	RPLL	199.999969
CPU_R5 freq (MHz)	500	IOPLL	499.999908
IOU_SWITCH freq (MHz)	267	IOPLL	249.999954
LPD_SWITCH freq (MHz)	500	IOPLL	499.999908
LPD_LSBUS freq (MHz)	100	IOPLL	99.999985
GEM_TSU freq (MHz)	250	IOPLL	249.999954
TIMESTAMP freq (MHz)	100	PSS_REF_CLK	33.333328
PCAP freq (MHz)	200	IOPLL	187.499969
DBG_LPD freq (MHz)	250	IOPLL	249.999954
ADMA freq (MHz)	500	IOPLL	499.999908
PL0 freq (MHz)	100	IOPLL	99.999985
AMS freq (MHz)	50	IOPLL	49.999992
ACPU freq (MHz)	1200	APLL	1049.999878
DBG FPD freq (MHz)	250	IOPLL	249.999954
DDR_CTRL freq MHz)	600.000	DPLL	599.999878
GPU freq (MHz)	600	DPLL	599.999878
GDMA freq (MHz)	600	DPLL	599.999878
DPDMA freq (MHz)	600	DPLL	599.999878
TOPSW_MAIN freq (MHz)	533.333	APLL	524.999939
TOPSW_LSBUS freq (MHz)	100	IOPLL	99.999985
DBG TSTMP freq (MHz)	250	IOPLL	249.999954

DDR Memory information

Parameter name	Value	Description
ENABLE	1	Enable the PS DDR Controller
DDR Interface freq (MHz)	1200	--
MEMORY TYPE	DDR 4	Type of memory interface
DM DBI	Components
BUS WIDTH	64 Bit	Data width of DDR interface, not including ECC data width
ECC	Disabled	Enables error correction code support
SPEED BIN	DDR4_2400R	Speed Bin
CL	16	Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL	12	CAS write latency setting in memory clock cycles
DDR AL	0	Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD	16	tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP	16	Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC	45.32	Row cycle time (ns)
T RAS MIN	32.0	Minimum number of memory clock cycles required between an Active and Precharge command
T FAW	30.0	Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH	16 Bits	Width of individual DRAM components
DEVICE CAPACITY	4096 MBits	Storage capacity of individual DRAM components
BG ADDR COUNT	1	Number of bank group address pins
RANK ADDR COUNT	0	Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT	2	Number of bank address pins
ROW ADDR COUNT	15	Number of row address pins
COL ADDR COUNT	10	Number of column address bits
C_DDR_RAM_HIGHADDR	0x7FFFFFFF	--

GT lanes information

Protocol

GT lane#

Ref Clk Sel

Ref freq (MHz)