/* 
 * File:   config.h
 * Author: J. K. Chytil
 *
 * Created on 12. duben 2013, 20:38
 */

#ifndef CONFIG_H
#define	CONFIG_H

    #pragma config FOSC = INTIO67   // Oscillator Selection bits (Internal
                                    // oscillator block)
    #pragma config PLLCFG = ON      // 4X PLL Enable
                                    // (Oscillator multiplied by 4)
    #pragma config PRICLKEN = ON    // Primary clock enable bit (Primary clock
                                    // enabled)
    #pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit
                                    // (Fail-Safe Clock Monitor disabled)
    #pragma config IESO = OFF       // Internal/External Oscillator Switchover
                                    // bit (Oscillator Switchover mode disabled)

    // CONFIG2L
    #pragma config PWRTEN = OFF     // Power-up Timer Enable bit (Power up timer
                                    // disabled)
    #pragma config BOREN = SBORDIS  // Brown-out Reset Enable bits (Brown-out  
                                    // Reset enabled in hardware only (SBOREN
                                    // is disabled))
    #pragma config BORV = 190       // Brown Out Reset Voltage bits (VBOR set
                                    // to 1.90 V nominal)

    // CONFIG2H
    #pragma config WDTEN = OFF      // Watchdog Timer Enable bits (Watch dog  
                                    // timer is always disabled. SWDTEN has no
                                    // effect.)
    #pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits
                                    // (1:32768)

    // CONFIG3H
    #pragma config CCP2MX = PORTC1  // CCP2 MUX bit (CCP2 input/output is
                                    // multiplexed with RC1)
    #pragma config PBADEN = ON      // PORTB A/D Enable bit (PORTB<5:0> pins are  
                                    // configured as analog input channels on
                                    // Reset)
    #pragma config CCP3MX = PORTB5  // P3A/CCP3 Mux bit (P3A/CCP3 input/output
                                    // is multiplexed with RB5)
    #pragma config HFOFST = ON      // HFINTOSC Fast Start-up (HFINTOSC output  
                                    // and ready status are not delayed by the
                                    // oscillator stable status)
    #pragma config T3CMX = PORTC0   // Timer3 Clock input mux bit (T3CKI is on
                                    // RC0)
    #pragma config P2BMX = PORTB5   // ECCP2 B output mux bit (P2B is on RB5)
    #pragma config MCLRE = EXTMCLR  // MCLR Pin Enable bit (MCLR pin enabled,
                                    // RE3 input pin disabled)

    // CONFIG4L
    #pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit
                                    // (Stack full/underflow will cause Reset)
    #pragma config LVP = ON         // Single-Supply ICSP Enable bit  
                                    // (Single-Supply ICSP enabled if MCLRE
                                    // is also 1)
    #pragma config XINST = OFF      // Extended Instruction Set Enable bit  
                                    // (Instruction set extension and Indexed
                                    // Addressing mode disabled (Legacy mode))

    // CONFIG5L
    #pragma config CP0 = OFF        // Code Protection Block 0 (Block 0
                                    // (000800-001FFFh) not code-protected)
    #pragma config CP1 = OFF        // Code Protection Block 1 (Block 1
                                    // (002000-003FFFh) not code-protected)
    #pragma config CPB = OFF        // Boot Block Code Protection bit  
                                    // (Boot block (000000-0007FFh) not
                                    // code-protected)
    #pragma config CPD = OFF        // Data EEPROM Code Protection bit
                                    // (Data EEPROM not code-protected)
    #pragma config WRT0 = OFF       // Write Protection Block 0 (Block 0
                                    // (000800-001FFFh) not write-protected)
    #pragma config WRT1 = OFF       // Write Protection Block 1 (Block 1
                                    // (002000-003FFFh) not write-protected)
    #pragma config WRTC = OFF       // Configuration Register Write Protection  
                                    // bit (Configuration registers
                                    // (300000-3000FFh) not write-protected)
    #pragma config WRTB = OFF       // Boot Block Write Protection bit  
                                    // (Boot Block (000000-0007FFh) not
                                    // write-protected)
    #pragma config WRTD = OFF       // Data EEPROM Write Protection bit
                                    // (Data EEPROM not write-protected)
    #pragma config EBTR0 = OFF      // Table Read Protection Block 0 (Block 0  
                                    // (000800-001FFFh) not protected from table
                                    // reads executed in other blocks)
    #pragma config EBTR1 = OFF      // Table Read Protection Block 1 (Block 1  
                                    // (002000-003FFFh) not protected from table
                                    // reads executed in other blocks)
    #pragma config EBTRB = OFF      // Boot Block Table Read Protection bit
                                    // (Boot Block (000000-0007FFh) not
                                    // protected from table reads executed in
                                    // other blocks)

#endif	/* CONFIG_H */