/*
 * File:   inits.c
 * Author: J. K. Chytil
 *
 * Created on 12. duben 2013, 20:37
 */


#include <pic18.h>
#include <htc.h>
#include <xc.h>
#include "hwprofile.h"



void init_ports(void)
{
    TRISAbits.TRISA2 = 0;   // Data outputs
    TRISAbits.TRISA3 = 0;
    TRISAbits.TRISA4 = 0;
    TRISAbits.TRISA5 = 0;

    TRISBbits.TRISB2 = 1;   // Data inputs
    TRISBbits.TRISB3 = 1;
    TRISBbits.TRISB4 = 1;
    TRISBbits.TRISB5 = 1;

    TRISBbits.TRISB0 = 1;   // Line sences
    TRISBbits.TRISB1 = 1;
    TRISCbits.TRISC1 = 1;

    DO0 = DO1 = DO2 = DO0 = 0;  // clear outputs
}

void init_perifs(void)
{

    INTCON &= (0 << GIEH);   // High Interupts Disabled
    INTCON &= (0 << GIEL);   // Low Interupts Disabled

    // ADC setting
    ANSELA = 0x03; // RA0, RA1 as analog rest of port digital
    ANSELB = 0x00; // all as digital
    ANSELC = 0x00; // all as digital
    ADCON2 = 0x3C; // left justify, 20TAD, FOSC/32
    ADCON1 = 0x00; // CCP Trig, Vref+ = AVDD, Vref- = AVSS
    ADCON0 = 0x01; // Ch: AN0, ADC: ON

    //SPI setting
    SSP1STAT = 0x00; // Input data sampled at middle of data output time
                     // Transmit occurs on transition from Idle to active clock
                     // state
    SSP1CON1 = 0x22; // Enables serial port and configures SCKx, SDOx, SDIx
                     // as the source of the serial port pins
                     // Idle state for clock is a low level
                     // SPI Master mode, clock = FOSC/64
    SSP1CON2 = 0x00; // Irelevant I2C setting only
    SSP1CON3 = 0x00; //If new byte is received with BF bit of the SSPxSTAT
                     // register already set, SSPxOV bit of the
                     // SSPxCON1 register is set, and the buffer is not updated
    SSP1MSK = 0x00;  // Irelevant I2C setting only
    SSP1ADD = 0x00;  // Irelevant I2C setting only

    INTCON |= (1 << TMR0IE);    // TMR0 Interupt Enabled
    INTCON |= (1 << INT0IE);    // INT0 Interupt Enabled
    INTCON &= (0 << RBIE);      // PORTB Interupt Disabled

    INTCON2 &= (0 << RBPU);     // All PORTB pull-ups are disabled
    INTCON2 |= (1 << INTEDG0);  // Interrupt on rising edge
    INTCON2 |= (1 << INTEDG1);  // Interrupt on rising edge
    INTCON2 |= (1 << INTEDG2);  // Interrupt on rising edge
    INTCON2 |= (0 << TMR0IP);   // High priority
    INTCON2 &= (0 << RBPU);     // Low priority

    INTCON3 &= (0 << INT2IP);   // Low priority
    INTCON3 |= (1 << INT1IP);   // High priority
    INTCON3 &= (0 << INT2IE);   // Disables the INT2 external interrupt
    INTCON3 |= (1 << INT1IE);   // Enables the INT1 external interrupt


    PIE1 &= (0 << ADIE);    // Disables the A/D interrupt
    PIE1 |= (1 << RC1IE);   // Enables the EUSART1 receive interrupt
    PIE1 &= (0 << TX1IE);   // Disables the EUSART1 transmit interrupt
    PIE1 |= (1 << SSP1IE);  // Enables the MSSP1 interrupt
    PIE1 &= (0 << CCP1IE);  // Disables the CCP1 interrupt
    PIE1 &= (0 << TMR2IE);  // Disables the TMR2 to PR2 match interrupt
    PIE1 &= (0 << TMR1IE);  // Disables the TMR1 overflow interrupt

    PIE2 = 0x00;            // PIE2 interupts disabled
    PIE3 = 0x20;            // PIE3 interupts disabled except RC2IE
    PIE4 = 0x00;            // PIE4 interupts disabled
    PIE5 = 0x00;            // PIE5 interupts disabled

    IPR1 = 0x00;            // IPR1 Low priority
    IPR2 = 0x00;            // IPR2 Low priority
    IPR3 = 0x00;            // IPR3 Low priority
    IPR4 = 0x00;            // IPR4 Low priority
    IPR5 = 0x00;            // IPR5 Low priority

    T0CON &= (0 << TMR0ON ); // Timer 1 OFF
    T0CON |= (1 << T08BIT ); // 8-bit timer
    T0CON &= (0 << T0CS );   // Internal instruction cycle clock
    T0CON &= (0 << T0CS );   // Increment on low-to-high transition on T0CKI pin
    T0CON |= (1 << PSA );    // TImer0 prescaler is NOT assigned. Timer0 clock
                             // input bypasses prescaler
    T0CON &= (0 << T0PS0 );  // 1:32 prescale value (NOT USED)
    T0CON &= (0 << T0PS1 );
    T0CON |= (1 << T0PS2 );
    TMR0L = 55;

    TXSTA1 &= (0 << TX91);    // 8-bit data
    TXSTA1 |= (1 << TXEN1);   // txd eanble
    TXSTA1 &= (0 << SYNC1);   // Asynchronous mode
    TXSTA1 &= (0 << SENDB1);  // Sync Break transmission completed
    TXSTA1 &= (0 << BRGH1);   // High Baud Rate Low Speed
    RCSTA1  &= (0 << SPEN1);  // UART enable
    RCSTA1 &= (0 << RX91);    // 8-bit data
    RCSTA1 |= (1 << CREN1);   // rxd enable
    BAUDCON1 &= (0 << BRG161); // 8 bit boud rate genertor
    BAUDCON1 &= (0 << ABDEN1); // Auto-Baud Detect mode is disabled
    SPBRG1 = 12;             // 8.000.000 / 9.600 / 64 - 1 = 12

    TXSTA2 &= (0 << TX91);    // 8-bit data
    TXSTA2 |= (1 << TXEN1);   // txd eanble
    TXSTA2 &= (0 << SYNC1);   // Asynchronous mode
    TXSTA2 &= (0 << SENDB1);  // Sync Break transmission completed
    TXSTA2 &= (0 << BRGH1);   // High Baud Rate Low Speed
    RCSTA2  &= (0 << SPEN1);  // UART enable
    RCSTA2 &= (0 << RX91);    // 8-bit data
    RCSTA2 |= (1 << CREN1);   // rxd enable
    BAUDCON2 &= (0 << BRG161); // 8 bit boud rate genertor
    BAUDCON2 &= (0 << ABDEN1); // Auto-Baud Detect mode is disabled
    SPBRG2 = 12;             // 8.000.000 / 9.600 / 64 - 1 = 12
}